This invention relates generally to an integrated circuit, and more specifically to an improved sense amplifier for use in an integrated circuit such as a memory or microprocessor chip.
In integrated circuits, transistors are frequently connected together into a network used for performing a logic function. This logic network will have several inputs, each input having a high or low voltage corresponding to binary logic states of logic high or logic low respectively, and will have an output having a voltage likewise corresponding to a binary logic state. This logic network is designed so that the output is a logical function of the inputs, and this function is established by the design of the logic network.
A common configuration for such a logic network is found in a programmable logic array (PLA) for a microprocessor. In a typical NOR PLA, as used in an MOS integrated circuit, many insulated gate field effect transistors (IGFETs) will be connected in parallel such that all drains are tied to a common output node and all sources are tied to a common virtual ground node (this virtual ground node provides a logic low reference for the network). This parallel network of IGFETs forms a row in the PLA. A typical PLA contains many such rows, and each row, for example, may consist of 32 or more IGFETs. A PLA row with parallel transistors provides a NOR logic function such that if one or more of the transistors in the row is conductive, then the row output will fall to a low voltage corresponding to a logic low due to discharging of the row output node by the conductive transistor(s); otherwise, the row output node will not be discharged and will remain at a high voltage corresponding to a logic high. This type of parallel transistor network is also commonly found in read-only memories (ROMs) and in other circuits requiring a NOR logic function with many inputs, for example zero-detect networks.
The output of a large parallel transistor network, such as used in a PLA or a ROM, is usually connected to a single-ended sense amplifier used to sense, or read, the logic state of the output as either a logic high or a logic low by detecting either a high or low voltage on the output. The common virtual ground node connected to the parallel transistors is usually connected to ground by a load transistor. Due to the large number of parallel transistors connected to a common output node, the capacitance of the output node slows output voltage changes considerably. Therefore, a limited-swing sense amplifier is frequently used to sense the output over a narrow voltage range, or swing, of say one or two volts and, thereby, increase sensing speed.
When using a limited-swing sense amplifier, the switchpoint of the amplifier must be approximately centered in the voltage swing of the output to be sensed. This is achieved by designing the sense amplifier to match the expected range of current through the logic network to be sensed. Because none, one, several, or all of the transistors in a parallel transistor network can be conductive, a sense amplifier used to sense the output of such a network must be designed to handle a wide current range. Prior sensing methods have relied upon a load transistor connected between a virtual ground node and a power supply ground node in order to limit current and thereby reduce the current range that must be handled by the sense amp. In previous circuits the control terminal of this load transistor has been connected to a constant voltage source or to a current terminal of the load transistor. Both of these approaches are not sufficiently adaptive to this wide current range, fail to significantly reduce this current range, and force the sense amplifier to be over-designed resulting in a waste of layout area on the integrated circuit. Also, the excessive current range associated with these prior approaches prevents adequate design control when positioning the switchpoint of the sense amplifier within the limited voltage swing of the logic network output, and therefore the response and noise margin of the sense amplifier vary excessively and unpredictably.
Other disadvantages of previous limited-swing sense amplifiers include the use of depletion transistors and the use of the same inverter for both sensing and feedback. Depletion devices are not available in typical CMOS integrated circuit processes. Using the same inverter to provide a feedback signal and to sense the logic state of a sense amplifier's input prevents the independent optimization of these two functions and therefore limits improvements in sensing speed.
The power consumption during a sensing operation of most limited-swing sense amplifiers is usually significant relative to other circuitry on an integrated circuit. Therefore, most sense amplifiers have been provided with a means for disablement such that power consumption is reduced significantly when no sensing is required. However, previous sense amplifiers have been designed with an arbitrary disable mode unresponsive to the state of the sense amplifier immediately preceding disablement. Often, during the operation of an integrated circuit, the inputs to a logic network having an output connected to a sense amplifier will not change during the disablement of the sense amplifier. In these cases it is desirable that the internal state of the sense amplifier, not just the output of the sense amplifier, be maintained while in the disabled mode. Previous sense amplifiers have not maintained this internal state and therefore have frequently suffered from noise glitches in the amplifier output when leaving the disabled mode.
Accordingly, a need exists for a sense amplifier to handle loads with a wide current range that retains stable response and adequate noise margin.